Field
The disclosure relates to electro-static discharge (ESD) protection for integrated circuits.
Background
State-of-the-art integrated circuits (IC's) feature increasingly dense circuitry and smaller device feature sizes due to continuous technology scaling. This trend increases the vulnerability of modern IC's to damage from electro-static discharge (ESD), making it important to provide adequate, robust ESD protection for modern IC's.
To ensure that an IC meets ESD requirements, predetermined test voltages may be externally applied across input/output (I/O) pins of the IC during manufacturing and testing. These test voltages may be generated according to various models known in the art for determining ESD compliance, e.g., charged-device model (CDM), human body model (HBM), machine model (MM), etc. When large test voltages are applied, the presence of parasitic inductances or resistances may undesirably cause large voltage drops to persist across critical terminals of the IC, potentially damaging sensitive circuitry.
Accordingly, it would be desirable to provide novel techniques for improving the robustness of ESD protection mechanisms in state-of-the-art IC's.